Feed: AnandTech
Feed Link: https://www.anandtech.com
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Title: Kioxia Details BiCS 8 NAND at FMS 2024: 218 Layers With Superior
Scaling

Date: Mon, 12 Aug 2024 10:00:00 EDT
Link: https://www.anandtech.com/show/21519/kioxia-d...

Kioxia's booth at FMS 2024 was a busy one with multiple technology
demonstrations keeping visitors occupied. A walk-through of the BiCS 8
manufacturing process was the first to grab my attention. Kioxia and Western
Digital announced the sampling of BiCS 8 in March 2023. We had touched
briefly upon its CMOS Bonded Array (CBA) scheme in our coverage of Kioxial's
2Tb QLC NAND device and coverage of Western Digital's 128 TB QLC enterprise
SSD proof-of-concept demonstration. At Kioxia's booth, we got more insights.

Traditionally, fabrication of flash chips involved placement of the associate
logic circuitry (CMOS process) around the periphery of the flash array. The
process then moved on to putting the CMOS under the cell array, but the wafer
development process was serialized with the CMOS logic getting fabricated
first followed by the cell array on top. However, this has some challenges
because the cell array requires a high-temperature processing step to ensure
higher reliability that can be detrimental to the health of the CMOS logic.
Thanks to recent advancements in wafer bonding techniques, the new CBA
process allows the CMOS wafer and cell array wafer to be processed
independently in parallel and then pieced together, as shown in the models
above.

The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5
and 162 layers in BiCS 6. The company decided to skip over BiCS 7 (or,
rather, it was probably a short-lived generation meant as an internal test
vehicle). The generation retains the four-plane charge trap structure of BiCS
6. In its TLC avatar, it is available as a 1 Tbit device. The QLC version is
available in two capacities - 1 Tbit and 2 Tbit.

Kioxia also noted that while the number of layers (218) doesn't compare
favorably with the latest layer counts from the competition, its lateral
scaling / cell shrinkage has enabled it to be competitive in terms of bit
density as well as operating speeds (3200 MT/s). For reference, the latest
shipping NAND from Micron - the G9 - has 276 layers with a bit density in TLC
mode of 21 Gbit/mm2, and operates at up to 3600 MT/s. However, its 232L NAND
operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm2.

It must be noted that the CBA hybrid bonding process has advantages over the
current processes used by other vendors - including Micron's CMOS under array
(CuA) and SK hynix's 4D PUC (periphery-under-chip) developed in the late
2010s. It is expected that other NAND vendors will also move eventually to
some variant of the hybrid bonding scheme used by Kioxia.

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