Feed: AnandTech
Feed Link: https://www.anandtech.com
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Title: CUDIMM Standard Set to Make Desktop Memory a Bit Smarter and a Lot
More Robust

Date: Fri, 21 Jun 2024 10:30:00 EDT
Link: https://www.anandtech.com/show/21455/making-d...

While the new CAMM and LPCAMM memory modules for laptops have garnered a
great deal of attention in recent months, it's not just the mobile side of
the PC memory industry that is looking at changes. The desktop memory market
is also coming due for some upgrades to further improve DIMM performance, in
the form of a new DIMM variety called the Clocked Unbuffered DIMM (CUDIMM).
And while this memory isn't in use quite yet, several memory vendors had
their initial CUDIMM products on display at this year's Computex trade show,
offering a glimpse into the future of desktop memory.

A variation on traditional Unbuffered DIMMs (UDIMMs), Clocked UDIMMs (and
Clocked SODIMMs) have been created as another solution to the ongoing signal
integrity challenges presented by DDR5 memory. DDR5 allows for rather speedy
transfer rates with removable (and easily installed) DIMMs, but further
performance increases are running up against the laws of physics when it
comes to the electrical challenges of supporting memory on a stick -
particularly with so many capacity/performance combinations like we see
today. And while those challenges aren't insurmountable, if DDR5 (and
eventually, DDR6) are to keep increasing in speed, some changes appear to be
needed to produce more electrically robust DIMMs, which is giving rise to the
CUDIMM.

Standardized by JEDEC earlier this year as JESD323, CUDIMMs tweak the
traditional unbuffered DIMM by adding a clock driver (CKD) to the DIMM
itself, with the tiny IC responsible for regenerating the clock signal
driving the actual memory chips. By generating a clean clock locally on the
DIMM (rather than directly using the clock from the CPU, as is the case
today), CUDIMMs are designed to offer improved stability and reliability at
high memory speeds, combating the electrical issues that would otherwise
cause reliability issues at faster memory speeds. In other words, adding a
clock driver is the key to keeping DDR5 operating reliably at high
clockspeeds.

All told, JEDEC is proposing that CUDIMMs be used for DDR5-6400 speeds and
higher, with the first version of the specification covering speeds up to
DDR5-7200. The new DIMMs will also be drop-in compatible with existing
platforms (at least on paper), using the same 288-pin connector as today's
standard DDR5 UDIMM and allowing for a relatively smooth transition towards
higher DDR5 clockspeeds.

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